In the modern physical design of very large scale integrated era, it is essential to design the chip, which works with multi-supply voltages to offer higher flexibility in controlling the energy and area of the chip. For multi-supply voltages chip, floorplanning has to estimate the chip area by incorporating energy efficient techniques. To achieve power optimization, multi-supply voltages circuits are partitioned into "voltage islands" where each island occupies an adjoining physical space and operates at one supply voltage. Though, previous papers deal floorplanning in different ways, none of the paper addresses voltage-island driven non-slicing floorplanning for mixed-size modules under the fixedoutline constraints. Since, floorplanning is a NP-hard problem, many optimization techniques were adopted in literature. In this work, a meta-heuristic optimization algorithm is used twice, with the aim of reducing the total chip area under fixed-die-outline constraints. First, the optimization algorithm is applied to floorplan the modules within a voltage-island then it is used to floorplan the voltageislands in an optimal way. A music-inspired harmony search algorithm and echo-location based bat algorithm are used as the meta-heuristic optimization algorithms. The experimental results show that our proposed approach provides efficient floorplanning, with reduced area and wire length.