The frequency doubler(FD) circuit has found immense use in digital CMOS systems. Such a circuit is especially useful in a clock distribution network where the clock signal can be distributed at a low frequency and multiplied (clock frequency made 2 or 4 times) at the blocks where a higher frequency is needed. This reduces the power consumption of the clock distribution network. Clock Frequency Multiplier circuits are also useful in chips to generate clock signals which are multiples of the available clock frequency generated by the oscillator. In this paper, we have designed a clock frequency doubler circuit suitable to reduce power consumption in a clock distribution network. The FD doubles fixed frequencies namely 250 MHz, 500MHz and 1 GHz. It also doubles frequency 10% around these fixed frequencies. The simulated circuit consumes only 411 pW of power and has a propagation delay of only 43.75nS.This circuit was then connected at the 4 leaves of a H-tree global CDN to double the clock frequency. This CDN achieved 50.2 % power savings when compared to a CDN distributing clock at the target frequency. © 2012 IEEE.