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Comparative performance analysis of XOR-XNOR function based high-speed CMOS full adder circuits
Bhavani Prasad Y, Harish Babu N, Ramana Reddy K.V,
Published in IEEE
Pages: 432 - 436
This CMOS Design, Complimentary Pass Transistor Logic Design and papers presents the realization of full adder designs using Complimentary XOR-XNOR Design in a single unit. The main motive of this paper is to determine the comparative study of power, delay, power delay product(PDP) of different Full adder designs using CMOS Logic Styles. Simulations results clearly determines that XOR-XNOR type Full adder Design is better compared to Complimentary CMOS style and Pass Transistor Design with respect to power, delay. Power Delay Product Comparison. The power delay product is also important parameter to determines the performance of the design. The XOR-XNOR implementation provides better performance and requires less number of transistors compared to other full adder designs. The implementation of design using GPDK 180nm with supply voltage of 1.8 V in Cadence Virtuoso Schematic Composer and simulations done by using Spectre Environment. © 2014 IEEE.
About the journal
JournalData powered by Typeset2014 International Conference on Reliability Optimization and Information Technology (ICROIT)
PublisherData powered by TypesetIEEE
Open AccessNo