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Computation-efficient image watermarking architecture with improved performance
Published in Elsevier Ltd
Volume: 84
This work presents a computation efficient image watermarking very large-scale integration (VLSI) architecture with improved robustness and throughput. The computational complexity is reduced by the incorporation of integer DCT, whereas the throughput is improved by the implementation of a four-stage pipeline architecture. Further, in the present work, the secret watermark bits are inserted in the DCT low-frequency coefficients using a mean adaptive threshold value, which not only results in a minimum degradation to the host image quality but also increases the robustness of the proposed algorithm. The VLSI implementation of the proposed algorithm using CadenceⓇ circuit design tools in 180 nm technology demonstrates an overall power consumption of 4.47 mW and a throughput of 2.5 Gbps that are better than the results reported in the literature. © 2020 Elsevier Ltd
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JournalData powered by TypesetComputers and Electrical Engineering
PublisherData powered by TypesetElsevier Ltd