PLL is a closed loop control system that synchronises its output signal in frequency as well as in phase with the input signal. PLL as Frequency Synthesizer in communication devices and as clock generator in SOCs are critical components where analog and digital signals interface on a single chip. Non ideal behaviour of charge pump (CP) has significant contribution to PLL output jitter and phase error. This work concentrates on reducing mismatch between UP and DOWN currents of CP and design of power efficient circuits. Proposed PLL operating frequency is 1.1GHz, tuning range is 210MHz to 2.3 GHz, and power consumption is 87.4532nW and achieved 99.98% power reduction. Integrated jitter is 26.73us. For design and implementation TSMC - 45nm is used. © Research India Publications.