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Defect detection and defect-tolerant design of a multi-port sram
R. Sushmitha, O.R. Nisha, , T. Vigneswaran
Published in Springer Science and Business Media Deutschland GmbH
Volume: 687
Pages: 523 - 537
Static random memory (SRAM)-based multi-port memory cell can perform multiple read and write operations simultaneously, thus increasing data throughput. With the continuous scaling of transistor feature size, designing low-power robust memories for microprocessors and investigating their failure characteristics become critical. In this work, we present a register file with a structure of three-port SRAM cell and a differential current-mode sense amplifier for read circuitry. We then study the fault models for resistive defect within the SRAM cell and its failure boundary. The presence of resistive-open defects has become more and more important, due to ever-increasing complexity. A read disturb fault for multi-port memories is tested on the faulty cell by simultaneous read operations with different numbers of ports. Resistive-open defects in embedded-SRAM core cells were identified, and a March test was proposed to cover the fault models. The proposed circuit is simulated and validated for 100 runs using Monte Carlo simulations. © Springer Nature Singapore Pte Ltd 2020.
About the journal
JournalData powered by TypesetLecture Notes in Electrical Engineering
PublisherData powered by TypesetSpringer Science and Business Media Deutschland GmbH