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Proceedings Article
Design and analysis of 8T SRAM with assist schemes (UDVS) in 45nm CMOSPublished in IEEE
2017
Topics: Dynamic voltage scaling (64)%64% related to the paper, Low voltage (60)%60% related to the paper, Voltage source (57)%57% related to the paper, Pass transistor logic (56)%56% related to the paper and CMOS (55)%55% related to the paper
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About the journal
| Journal | Data powered by Typeset2017 International Conference on Circuit ,Power and Computing Technologies (ICCPCT) |
|---|---|
| Publisher | Data powered by TypesetIEEE |
| Open Access | 0 |
Authors (1)
Satheesh Kumar S- ASIC implementation of high speed pipelined DDR SDRAM controller
- Design and analysis of 8T SRAM with assist schemes (UDVS) in 45nm CMOS
- A SEU Hardened Dual Dynamic Node Pulsed Hybrid Flip-Flop with an Embedded Logic Module
- SEU hardened DFF and 4 bit johnson counter using quatro latch in 45 nm technology
