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Design and analysis of an ultra-l ow power single electron transistor based binary multiplier
Published in Institute of Advanced Scientific Research, Inc.
Volume: 11
Issue: 8 Special Issue
Pages: 2346 - 2365
This paper explores the characteristics of the single-electron transistor as well as to realize its application in the field of digital arithmetic circuits. The single-electron transistor is a Nanodevice which can operate at low voltage and offers low power consumption. The single-electron transistor amplifies current by controlled electron tunneling and maintains its scalability even on an atomic scale. Here, scalability means that the performance of the device increases with a reduction in the device dimensions. Single gate SET offers low current drivability and low power due to single-electron tunneling from source to quantum dot and quantum dot to drain. In double-gate SET both the gates control the electron tunneling, which improves the speed and reduce the power. The low current drivability and operating speed of the single-electron transistor could be enhanced by combining SET with MOSFET known as Hybrid SET. In this paper, we used Verilog A code to model symmetric SET, which operates at room temperature and analysed the I-V characteristics under cadence simulation environment. We have designed binary multiplier using devices like single gate SET, double gate SET, hybrid single gate SET and hybrid double gate SET and we have examined the performance of these multipliers in terms of area, delay and power consumption. The simulation results prove that double gate SET based multiplier provides ultra-low power consumption and hybrid double gate SET based multiplier offers high operating speed. © 2019, Institute of Advanced Scientific Research, Inc. All rights reserved.
About the journal
JournalJournal of Advanced Research in Dynamical and Control Systems
PublisherInstitute of Advanced Scientific Research, Inc.