An energy efficient and novel Charge Sharing Complementary Pass Transistor Adiabatic Logic (CSCPAL) operated by four phase power clock is proposed. It realizes low switching noise and incurs low leakage power. FinFETs are ideal devices for low power circuit design due to their enhanced properties of reduced short channel effects and lower leakage current. The circuits are designed using 32nm FinFET models and are simulated using Cadence® Virtuoso design tools. Efficiency of FinFET based CSCPAL is compared with FinFET based 2N2N2P, 2N2P and PFAL designs found in the literature. Energy consumption of CSCPAL Inverter/Buffer, AND and XOR sub modules used in the design of 8-bit Carry Lookahead Adder circuits have been compared with the 2N2P, 2N2N2P and PFAL based circuit counterparts. 8-bit CLA is taken as a benchmark circuit for validation of energy efficiency. © 2019 IEEE.