The paper presents the design of the program counter for low power and high performance. Two approaches namely, 1) finite state machine logic based and 2) incrementer based logic have been employed. The designs have been implemented and the comparison between the two design methodologies has been made. The finite state machine logic based design uses flip flops and multiplexers, while the incrementer based design employs the incrementer circuit and registers. The average power consumed by the program counter designed using FSM based logic is 64.72% less as compared to that of Incrementer based design at 1 GHz operation frequency. The delay incurred by the incrementer based design is 34.92% lesser compared to that of the finite state machine based approach, however at the cost of increase in the area. The designs have been implemented using industry standard Cadence® EDA tools and simulated using 90nm technology files. © 2014 IEEE.