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Design and Development of BIST Architecture for Characterization of S-RAM Stability
Krishna Chaitanya M,
Published in Indian Society for Education and Environment
Volume: 9
Issue: 21
Objectives: The objective is to find the optimum SNM of SRAM and then a BIST architecture is designed and implemented to test the SRAM cells varying the voltage of the bit lines. Methods/Analysis: In this paper we use a detection technique which is digitally programmable to detect the defective SRAM cells by using some additional set of SRAM cells to change the bitline voltage and then apply stress to the CUT. Findings: By using this programmable detection technique, cells can be tested even after the fabrication and accordingly one can find out the bit line voltages at which even weak and bad cells can be made useful. Improvement: The main advantage of programmability is that we can maintain considerable tradeoffbetween test yield and quality. The results at the end will justify the effectiveness of the BIST architecture.
About the journal
JournalIndian Journal of Science and Technology
PublisherIndian Society for Education and Environment
Open Access0