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Design and Device Characteristic Analysis of A Triple Material Double Gate (TMDG) Strained Channel MOSFET
J. Sharma, R. Pandey,
Published in Institute of Electrical and Electronics Engineers Inc.
2018
Abstract
In this paper A Triple Material Double Gate (TMDG) n-MOSFET with strained Si (s-Si) channel is proposed. The proposed MOSFET consist of two gate electrodes. Both gate electrodes have three materials with different work-functions. Channel region of MOSFET has strained Si to enhance mobility of charge carriers. Using ATLAS, which is a 2 dimensional device simulator, we have extracted threshold voltage (Vth) of proposed device along with DG MOSFET and DG strained Si channel MOSFET from transfer characteristics of MOSFETs. Trans-conductance (gm) and DIBL analysis of the MOSFET structures is also done in this paper. The strain in Si channel affects effective mass and inversion layer mobility of electrons of Channel which leads to increased drain current. In DG strained MOSFET, As compared to DG MOSFET, improvement in current is observed but the threshold voltage (Vth) of the MOSFET reduces and also DIBL is increased. Reduced threshold voltage is a short channel effect (SCE) which takes place due to reduced potential barrier between source and drain in nanometer regime. TMDG structure leads to increased threshold voltage because of surface potential profile modifications. Surface potential profile of TMDG MOS shows two steps due to three materials used in both the gate electrodes, as a result drain conductance reduces. Reduced drain conductance leads to reduced SCEs like DIBL and Vth lowering. Maximum electric field at the drain electrode also reduces in TMDG structure which minimizes HCE. Threshold voltage also increases in the proposed structure as compared to DG strained MOSFET. Surface potential profile, threshold voltage (Vth), trans-conductance (gm) and DIBL variation are observed in TMDG s-Si n-MOSFET. Proposed MOS device incorporates advantages of both TMDG MOS and strained Si channel MOSFET device to increase performance of high density chips in MOS VLSI technology. © 2018 IEEE.