This paper deals with design and implementation of an end to end MIMO system. Least Square (LS) channel estimation and QPSK techniques are used to implement 2×2 MIMO system.The design is modeled using MATLAB to derive the required specification. MIMO model is developed using Verilog and synthesized for area, power and speed. The HDL code for 2×2 MIMO system is simulated, synthesized and implemented on Virtex2Pro FPGA board and the results are validated against Matlab. The design is targeted on 7 and 30 million gate Virtex to compare its hardware performance. Based on the results obtained, hardware constraints for ASIC implementation is derived and implemented using Synopsys ASIC flow. Channel estimation and QPSK models have the maximum delay, the critical paths in these models are identified and redesigned to minimize the delay using buffer insertion technique. The results are verified for its functionality. With the modifications performed the frequency of opertion is increased to 13.388MHz from 7.27MHz. © EuroJournals Publishing, Inc. 2009.