Dube A

Sreshta S

Singh D.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

&nbsp;

&nbsp;

VIT University

Design and Implementation of Dual-Pair-Single-Rail Checker with Carry Select Adder

2018 2nd International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE)

This paper focuses on the design of self-checking carry select adder (CSTA) using FinFET devices. The CSTA adder comprises of Boolean to Excess-1 converter and D-latch. While going for multi-bit addition, it is more prone to various types of faults. Hence, the design of a self-checking CSTA is more prone to faults. This paper focuses on the design of 4-bit CSTA using FinFET and a sum bit checker design using FinFETs. The simulations are carried out using Cadence® Virtuoso platform with 32-nm FinFET technology library. The results demonstrate a device overhead of 12 and slight increase in delay and power consumption. However, the purpose of the carry checker design has a great impact on preventing the propagation of faults and ultimately ends in fault-free circuit. © Springer Nature Singapore Pte Ltd. 2018.

Lecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications

Design and Implementation of Multi-bit Self-checking Carry Select Adder

Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA. © 2010 IEEE.

Journal	Data powered by Typeset2018 2nd International Conference on Micro-Electronics and Telecommunication Engineering (ICMETE)
Publisher	Data powered by TypesetIEEE
Open Access	0