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Design and implementation of a DCTQ processor for low area, power and high performancePublished in Institute of Electrical and Electronics Engineers Inc.
2017
Pages: 1623 - 1626
A fast, area efficient and low power DCTQ processor for image compression has been proposed in this paper. Verilog HDL is used for capturing the design, simulated with Xilinx 12.4 to verify the design. It is then synthesized and implemented using Synopsys Design Vision tool. The area and power report shows the usefulness of the design for image compression purposes. © 2016 IEEE.
Topics: Image compression (60)%60% related to the paper, Verilog (59)%59% related to the paper, Algorithm design (53)%53% related to the paper and Discrete cosine transform (53)%53% related to the paper
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About the journal
| Journal | Data powered by TypesetInternational Conference on Signal Processing, Communication, Power and Embedded System, SCOPES 2016 - Proceedings |
|---|---|
| Publisher | Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc. |
Authors (1)
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