Binary multiplier is one of the most time and power consuming architectures in an ALU. The performance efficiency of complex computations is determined by the multiplier algorithm used. Design of an efficient multiplier thus becomes important. An attempt has been made to implement an efficient multiplier using ancient computational techniques using charge recovery logic. This circuit is compared against the existing vedic multiplier circuits designed using conventional CMOS logic, to validate our claim. A 4 x 4 vedic multiplier using 2 N-2P type of charge recovery logic structure is implemented. The design and verification have been done using industry standard SPICE tools. The simulation results depict reduction in the average power consumption by 77.66 %. © 2013 Springer.

V S Kanchana   Bhaaskaran

Electronics

School of Electronics Engineering

Chennai Campus

Appasaheb B.R

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Design and Implementation of an Efficient Multiplier Using Vedic Mathematics and Charge Recovery Logic

Lecture Notes in Electrical Engineering Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013)

Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

Journal of Circuits, Systems and Computers

Low Power, High Speed and Area Efficient Binary Count Multiplier

Divider is an inevitable and basic hardware module employed in advanced and high speed digital signal processing (DSP) units of high precision. It is widely used in radar technology, communication, industrial control systems and linear predictive coding (LPC) algorithms in speech processing. This paper proposes a fast, low power and cost effective architecture of a divider using the ancient Indian Vedic division algorithm. The merits of the proposed architecture are proved by comparing the gate count, power consumption and delay against the conventional divider architectures. The validation of the proposed architecture has resulted in 52.93 percent reduction in power dissipation against comparison with conventional divider using repeated subtraction. The designs were implemented using industry standard Cadence® software using 45nm technology library. The design has been validated on FPGA Spartan-3E kit. The validation results show appreciable reduction in circuit latency and in Look-Up-Table (LUT) utilization using proposed Vedic divider than the conventional divider. © 2014 IEEE.

2014 International Conference on Advances in Computing, Communications and Informatics (ICACCI)

Low power divider using vedic mathematics

The novel pre-resolve and Sense Adiabatic Logic (PSAL) is a less complex quasi-adiabatic logic circuit usable for frequency range from 100 KHz to 500 MHz. It employs a large height pre-resolved nMOS structured tree and a differential sensing logic. The logic realizes superior energy efficiency through reduced silicon area requirement, low circuit latency, glitch-free output and less switching transients. Significant reduction in switched capacitance realizes enhanced speed performance. Furthermore, evaluation of more than one level of gate (or a complex gate) in each phase makes use of less number of buffers possible, in the adiabatic pipeline. With circuit latency being a major impediment of four-phase adiabatic logic styles, PSAL achieves better throughput and reduced critical path length leading to improved frequency performance. The nMOS structured cascode tree and differential sensing logic help overcome the incomplete charge-recovery and the floating output node problems prevalent in adiabatic logic structures. Full custom and modular flow is adopted in the circuit designs. The design is proved energy-efficient for both low and high frequency ranges of the order of 200 KHz and 500 MHz, respectively for an 8-bit multiplier. Full-custom designs are done using 350 nm CMOS technology library from Austria Micro Systems. Performance efficiency is proved through comparisons with static CMOS and PFAL equivalent circuits through extensive post-layout simulations.

PRE-RESOLVE AND SENSE ADIABATIC LOGIC FOR 100 KHZ TO 500 MHZ FREQUENCY CLASSES

VLSI design techniques are the key to reengineering the digital gadgets of any kind which are needed to be operated with lower power to ensure a longer backup time. Power reduction in Arithmetic Logic Unit (ALU) is needed for this requirement. Multipliers and adders are the most important structures which use a larger fraction of power in such arithmetic units. This paper analyses the use of an ancient (or Vedic) mathematical approach for building an ALU. Validation for the low power operation of the circuit is made by designing a conventional CMOS counterpart whose power is compared with our ancient arithmetic design. A 4x4 multiplier based on the Vedic and Conventional methods have been designed using SPICE simulator. Simulation results depict the Vedic design incurring 29% of reduced average power. © 2011 IEEE.

2011 International Conference on Process Automation, Control and Computing

Evaluation of the Conventional vs. Ancient Computation Methodology for Energy Efficient Arithmetic Architecture

The paper presents the design, evaluation and performance comparison of cell based, low power adiabatic adder circuits operated by two-phase sinusoidal power clock signals, as against the literatures providing the operation of various adiabatic circuits, focusing on inverter circuits and logic gates, powered by ramp, three phase and four phase clock signals. The cells are designed for the quasi-adiabatic families, namely, 2N2P, 2N2N2P, PFAL, ADSL and IPGL for configuring complex adder circuits. A family of adiabatic cell based designs for carry lookahead adders and tree adders were designed. The simulations prove that the cell based design of tree adder circuits can save energy ranging from 2 to 100 over a frequency range of operation of 2MHz to 200MHz against the static CMOS circuit implementation. The Schematic Edit and T-Spice of Tanner tools formed the simulation environment. © 2006 IEEE.

Journal	Data powered by TypesetLecture Notes in Electrical Engineering Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013)
Publisher	Data powered by TypesetSpringer India
ISSN	1876-1100
Open Access	No