In this paper, we present the design of Advanced Peripheral Bus (APB) controller (or APB Bridge). UART as an APB slave has been used in the design. Linear Feedback shift register (LFSR) module has been included in the UART design for data security. We have also compared APB Bridge design compatible with AMBA Specification (Rev 2.0) and APB Bridge design compatible with AMBA 3 APB Specification (v1.0) for power and area constraints have been done. Design of APB Bride with AMBA3 APB save 6% power and 10% area over the one designed with AMBA2 APB. © 2014 IEEE.

Sivasankaran K

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Paunikar A

Gavankar R

Umarikar N

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Design and implementation of area efficient, low power AMBA-APB Bridge for SoC

2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)

International Journal of Science and Research (IJSR)

FPGA Implementation of AHB to APB Protocol

2012 International Conference on Communication Systems and Network Technologies

FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL

Journal	Data powered by Typeset2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE)
Publisher	Data powered by TypesetIEEE
Open Access	No