Flash ADCs includes multiple regenerative Dynamic comparators. These regenerative comparators is required as a result of it utilizes low-power, have sensible sampling rates, and lesser areas. Flash ADCs is constructed using double tail comparator, fat tree encoder for its low power, high speed in ultra deep submicron CMOS technologies. In this paper a double tail dynamic comparator is implemented and achieved maximum clock frequency of 2.42 GHz with power consumption of 1.8 u W. Based on the previous designs the implemented comparator design is the best performance oriented design compared to others. By using implemented comparator design flash ADC is performed with the combination of encoder. 3-bit flash ADC is implemented using cadence virtuoso in GPDK 90nm CMOS process technology. Simulation and experimental results shows that 3-bit flash ADC consumes power of 3.2m W with maximum sampling frequency of 290 MHz at 0.7v supply voltage. © Research India Publications.