In practical scenarios, the need for efficient adaptive filters has been increasing tremendously because of the need to remove a signal whose frequency response is unknown. The Least Mean Square (LMS) algorithm is an adaptive filter algorithm used in many applications related to adaptive signal processing. The LMS algorithm describes the adjustment of filter coefficients based on different time instances. The major digital components required to design efficient adaptive filters are adders and multipliers. This paper presents a near optimum, low-complexity, low power and high-speed reconfigurable adder architecture based on reversible computing methodology suitable for the adaptive filter. Reversible circuits have less power dissipation as they restore the information reversibly. The LMS algorithm uses the proposed reversible carry select adder to reduce the power consumption, and increase the speed of operations. The proposed architecture has been implemented and tested on a Virtex 2 xc2vp2-6fg256 field-programmable gate array (FPGA). The proposed novel reconfigurable adaptive filter implementation using reversible carry select adder offers good area, power, and speed improvement compared to existing reconfigurable adder implementations. © 2019, Institute of Advanced Scientific Research, Inc.. All rights reserved.