This paper presents an error compensation bias circuit added to a modified encoded booth multiplier to produce a high accuracy fixed-width multiplier. Fixed-width multiplier is employed in many digital signal processing applications, as most of these systems employ iterative structures with fixed precision. The design has been implemented in TSMC 180nm technology. The design is 14.6% faster than the fixed-width multipliers. The design has 37.2% less truncation error as compared to direct truncated fixed width multiplier (DTFM). The design is embedded with operand isolator technique to ensure low power operation when employed in DSP applications. © 2014 IEEE.