In this, we proposed improved area - efficient weighted modulo 2n+1 adder. This is achieved by modifying existing diminished-1, weighted modulo 2n+1 adder to incorporate simple correction schemes .Proposed adder is designed using area efficient parallel prefix structure and carry select adder. Proposed adder can produce modulo sums within the range (0, 2n) that is more than the range (0, 2n-1) produced in existing diminished-1 modulo 2n+1 adders. Modular adder is designed using verilog HDL and implemented using 45 nm technology and the area required by the proposed adder is lesser than the existing diminished-1,weighted modulo 2n+1 adder. © 2006-2014 Asian Research Publishing Network (ARPN).