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Design and implementation of low power floating point arithmetic unit
Kukati S, , Sujana D.V, Bharathi V, Udaykumar S, Shilpa K, , Sujana D.V, Sahoo S.K.
Published in IEEE
Volume: 9
Issue: 3
Pages: 339 - 346
This paper proposes implementation of IEEE floating point (FP) multiplication and division. Arithmetic on IEEE FP numbers imposes more challenges compared to fixed-point arithmetic. These particularly include the simultaneous computation of normalization and rounding. We show the efficient way of solving these challenges for the implementation of floating point (FP) addition and multiplication. The proposed designs aim at reducing power dissipation. Here multi threshold voltage technique is used for reducing power dissipation. The proposed implementations are according to the IEEE 754 FP standard. © Research India Publications.
About the journal
JournalData powered by Typeset2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE)
PublisherData powered by TypesetIEEE
Open AccessNo