This paper proposes implementation of IEEE floating point (FP) multiplication and division. Arithmetic on IEEE FP numbers imposes more challenges compared to fixed-point arithmetic. These particularly include the simultaneous computation of normalization and rounding. We show the efficient way of solving these challenges for the implementation of floating point (FP) addition and multiplication. The proposed designs aim at reducing power dissipation. Here multi threshold voltage technique is used for reducing power dissipation. The proposed implementations are according to the IEEE 754 FP standard. © Research India Publications.

Dhanabal R

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Jayakrishnan P

Kukati S

Sujana D.V

Bharathi V

Udaykumar S

Shilpa K

Sahoo S.K.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Design and implementation of low power floating point arithmetic unit

2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE)

Nowadays reversible logic circuits are gaining fascinating attraction in many fields. Main aim of using reversible gate is that we can easily get input from output. In this paper, we are using some reversible gates which help us to perform logical and arithmetic operations. Reversible gates namely TSG gate performs 1-bit addition with carry. This is the first reversible gate which alone can acts as full adder. PV gate, Fredkin gate is used to perform logical operations like AND, OR. So here we are designing 1-bit alum using pass transistor with virtuoso tool of cadence. Based on analysis of the result, this design using reversible gates is better than that using the irreversible gates. © Springer India 2016.

Proceedings of the International Conference on Soft Computing Systems Advances in Intelligent Systems and Computing

Design of Reversible Logic Based ALU

Reversible quantum logic plays an important role in quantum computing. This paper proposes implementation of MAC unit using reversible logic. We have discussed all the elementary reversible logic gates which are used in the design. Here, 4 × 4 irreversible MAC has been compared with reversible MAC and it has been found that, there is 25.6% reduction in the power consumption. The design has been simulated using ModelSim and synthesized using Cadence RTL compiler. © Springer India 2016.

Implementation of MAC Unit Using Reversible Logic

There were no limits for speed of operation of arithmetic/logical circuits. One can always try to increase their speed. There were many proposed algorithms, which would work fast to specified arithmetic operations. So, there is the need for the implementation of a faster design by putting these fastest algorithms in a single ALU. The carry-select adder with K-S algorithm is found to be one of the fastest algorithms for addition and Urdhva-Tiryagbhyam Karastuba algorithm for multi- plication, which are the most important operations in any central processing unit. We have used QUARTUS-II software. This design can be used where high speed computation is needed. This design would work for unsigned, fixed point, 8-bit operations. We have taken the different adder circuits and compared their perfor- mance. These circuits are the basic elements or building blocks of an ALU. The circuits have been simulated using 90 nm technology of Cadence and Quartus II EP2C20F484C7. Adders can be implemented using EX-OR/EX-XNOR gates, transmission gates, HSD (High Speed Domino) technique, domino logic. Parallel feedback carry adder, ripple carry adder, carry look ahead adder, carry-select adder are some of the adders that been implemented using Cadence and Quartus-II. We found that 10T PFCA is efficient compared to 11 T PFCA to some extent. Adders © Springer India 2016.

Design of Basic Building Blocks of ALU

To represent very large or small values, large range is required as the integer representation is no longer appropriate. These values can be represented using the IEEE-754 standard based floating point representation. This paper presents high speed ASIC implementation of a floating point arithmetic unit which can perform addition, subtraction, multiplication, division functions on 32-bit operands that use the IEEE 754-2008 standard. Pre-normalization unit and post normalization units are also discussed along with exceptional handling. All the functions are built by feasible efficient algorithms with several changes incorporated that can improve overall latency, and if pipelined then higher throughput. The algorithms are modeled in Verilog HDL and the RTL code for adder, subtractor, multiplier, divider, square root are synthesized using Cadence RTL complier where the design is targeted for 180nm TSMC technology with proper constraints. © 2013 IEEE.

2013 IEEE CONFERENCE ON INFORMATION AND COMMUNICATION TECHNOLOGIES

VLSI implementation of a high speed single precision floating point unit using verilog

2009 19th IEEE Symposium on Computer Arithmetic

Advanced Clockgating Schemes for Fused-Multiply-Add-Type Floating-Point Units

IEEE Transactions on Computers

Hardware Designs for Decimal Floating-Point Addition and Related Operations

IET Computers & Digital Techniques

High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4

2007 National Radio Science Conference

High-Speed, Area-Efficient FPGA-Based Floating-Point Arithmetic Modules

Journal	Data powered by Typeset2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE)
Publisher	Data powered by TypesetIEEE
ISSN	09734562
Open Access	No