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Design and implementation of SoC Wire Codec for space applications
Published in IEEE
Pages: 480 - 485
Dynamic Partial Reconfiguration (DPR) permits a particular portion of an FPGA to be reconfigured while the remaining part continues to operate. In order to communicate between static (which is running during the whole application runtime and stores all critical interfaces ) and dynamic regions we propose dedicated Network-on-Chip (NoC) approach called System-on Chip (SoC) Wire. This SoC Wire provides guaranteed system qualification with hot-plug ability, high speed point-to-point connection and support of the adaptive macro-pipeline as compared to the Bus Macros which suffers from more area and power consumptions. In this paper we designed the SoC Wire Codec by using Verilog HDL code. The implementations have been done using XILINX FPGA platform and the functionality of the system is verified using Modelsim simulation and board level ChipScope PRO. The presented SoC Wire Codec design utilizes 13% reduced area and ultimately reducing cost of the design. © 2011 IEEE.
About the journal
JournalData powered by Typeset2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies
PublisherData powered by TypesetIEEE
Open AccessNo