In this paper, the effects of Single Event Transients (SETs) due to heavy-ion strike in Double-Gate (DG) MOSFET is studied through simulations. Based on the understanding through simulation studies, an optimized device design is proposed to reduce these effects. The charge deposition by the heavy-ion striking at the center of the channel and the transport of the released charge carriers towards the drain are simulated. The DG-MOSFET is optimized through channel doping, varying silicon thickness and back gate bias to reduce the effects of SETs. © Springer Nature Switzerland AG 2019.

Bindu B

Electronics

School of Electronics Engineering

Chennai Campus

Mohammed Aneesh Y

Pasupathy K.R

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Design and Optimization of Double-Gate MOSFET to Reduce the Effects of Single Event Transients

Springer Proceedings in Physics The Physics of Semiconductor Devices

Electronic circuits operated in radiation environment such as space are adversely affected by the ionizing radiation. The effects include generating a transient current, altering threshold voltage and other device characteristics, and lattice damage. Of these, transient current can result in immediate change in device/circuit behaviour resulting in malfunction. This will be recoverable based on the energy and type of the ion. Thus, a better understanding of single-event effects is very important to operate the electronic circuits in the radiation environment. This paper reviews the existing methodologies to simulate the propagation of single-event transient (SET) in digital circuits and their shortcomings. An improved simulation methodology which can reproduce even the tail portion of the SET current as observed in three-dimensional technology computer aided design (TCAD) mixed-mode simulations is also proposed in this paper. This is obtained by modifying an existing simulation technique based on switch and resistor using varying resistance. The proposed technique is simple and easy to implement the SET propagation in any circuit simulator. After integrating this proposed simulation technique in circuit simulator SPECTRE, the propagation of SET, and its effects in delay locked loop (DLL) are analysed. The strike of SET in voltage-controlled delay line (VCDL) results in duty cycle error and missing clock pulse error at the DLL output. Also, the results show that the first few stages of the VCDL are more vulnerable than the rest for LETs (linear energy transfer) more than 60 MeV-cm2/mg. For LETs less than 60 MeV-cm2/mg, last delay stage has more vulnerability. © 2017 IETE.

IETE Technical Review

A Review on Circuit Simulation Techniques of Single-Event Transients and their Propagation in Delay Locked Loop

IEEE Transactions on Device and Materials Reliability

Single-Event Pulse Broadening After Narrowing Effect in Nano-CMOS Logic Circuits

IEEE Transactions on Nuclear Science

Single Event Transients in Digital CMOS—A Review

3-D Simulation Analysis of Bipolar Amplification in Planar Double-Gate and FinFET With Independent Gates

Modeling and Simulation of Single-Event Effects in Digital Devices and ICs

Journal	Data powered by TypesetSpringer Proceedings in Physics The Physics of Semiconductor Devices
Publisher	Data powered by TypesetSpringer International Publishing
ISSN	0930-8989
Open Access	No