This paper presents the design of Wishbone compliant memory controller which behaves as interface between processor and memory. Memory controller is a digital circuit which manages the flow of data to and fro from the processor to the memory. Instead of processor handling all the read and write operations into the memory, it allocates its work to memory controller so that processor can do some other work during the same time. This in turn leads to increase processor’s performance. The memory controller used in this work supports synchronous static random access memory (SSRAM), synchronous dynamic random access memory (SDRAM), and synchronous chip select device. It also deals with the verification and functional coverage of the controller. The design part has been done using Xilinx ISE tool, and the verification part has been done using Mentor Graphics Questa Sim 10.0b. © 2018, Springer Nature Singapore Pte Ltd.