This paper presents design of 4 Bit Flash Analog to Digital Converter using a latest comparator for voltage comparison called Threshold Modified Comparator Circuit (TMCC) and NOR ROM encoder in cadence environment using 90nm CMOS Technology. The TMCC comparators are designed to optimize the input offset voltages by systematically and consistently varying the transistor sizes of the differential transistor pair, nothing like the usual differential voltage comparators designed to reduce the input-offset voltage error due to the mismatches in a differential transistor pair. The TMCC comparators are used to compare very small voltages, to eliminate total resistor ladder network, and to improve linearity in an ADC. Because of complete elimination of resistor ladder it can reduce area and consume less power. The power consumption of proposed ADC is 4.43mW whereas operating input frequency of 2MHz and a operating voltage of 1.8 Volt. © 2015 IEEE.