Faithful reproduction of digital images is the key requirement in image storage and transfer systems. The IEEE 1180-1990 and CCITT have recommended the required error specifications for DCT/IDCT processors. In this paper, the input pixel data (gray-scale) are represented as rational fractions by normalization. The range and bit size required for representing the data and cosine-coefficient (CC) were obtained through analysis of Chen's algorithm based 8 × 8 2DDCT. A model of DCT processor was developed in MATLAB, which incorporated the effects of the error due to fixed-integer-point and a fixed word length representation. The error and range analysis ensured that 16-bits for data and 13-bits for CC were sufficient to compute the 2D-DCT without compromising the accuracy. The arithmetic functional units required for implementing 8 × 8 2D-DCT processor were designed with the proposed data formats, namely: pixel normalization block, signed adder/subtractor and CC multipliers. The pipelined 8 × 8 DCT core with 8-clock latency was implemented using TSMC 45nm, 1P6M technology. The implemented core takes 15.8k gates, consumes only 8.56mW of power at 125MHz and processes the image at one Giga pixels/s. The FPGA implementation of the 2D-DCT confirms the error performance as 71dB PSNR for a sample image of size 1280 × 720 pixels. © 2015 Pushpa Publishing House, Allahabad, India.