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Design of a passive damped filter for harmonic reduction in multilevel inverters used in PV applications
Published in IEEE
passive filter is connected at the output of a voltage source inverter in standalone and grid connected applications to reduce harmonics. This paper presents a parameter design procedure of a passive LC filter containing a damping resistor for a five level inverter. The work aims to improve the output waveforms of the inverter and reduce the total harmonic distortion content on its output waveforms. The design is carried out with an objective to provide better attenuation of switching frequency harmonics and effective suppression of resonant peaks. All equations derived are simple and accurate which provides insight into design of passive LC filter with resistance damping without cumbersome algorithms. This work uses a modified methodology to arrive at the value of damping resistance for harmonic reduction with minimum losses. The modified method considers quality factor, resonant peaking, harmonic attenuation rate and power loss in the damping branch to select the resistance value. Simulation and experimental results are included to analyse the harmonic distortion on the output waveforms. Experiments have been conducted on a five level cascaded H-Bridge inverter set up. The modulation scheme is implemented on a FPGA platform using SPARTAN 3E-XCS250E controller. A very good agreement is seen between the experimental and simulation results of the developed filter design. The results prove the effectiveness of the resistive damped passive filter for multilevel inverters. © 2018 IEEE.
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JournalData powered by Typeset2018 IEEE 8th Power India International Conference (PIICON)
PublisherData powered by TypesetIEEE
Open Access0