A novel scheme for the design of an area and power efficient digital finite impulse response (FIR) filter for digital signal processing (DSP) application's is studied in this paper. The key blocks of the filter are multipliers and adders, in which multiplier is the one which occupies the major silicon area and consumes more power. In general, the multiplication operations are performed by the shift and add logic. Most of the DSP applications demand faster adders for its arithmetic computations. Carry Select Adder (CSLA) is a well known adder for its faster computation time. Recently, an efficient Carry Select Adder (CSLA) was proposed which significantly reduce the area and power by eliminating the redundant logic gates at each bit level. In this paper, we propose an area and power efficient FIR filter implementation using modified Multiply and Accumulate (MAC) unit. The performance analysis of the proposed FIR filter is estimated with the MAC unit realized by the conventional adder and the modified carry select adder as well. The proposed FIR filter architecture with length of 5-tap and 9-tap are developed using Verilog HDL and implemented using SAED 90nm CMOS technology. The ASIC synthesis results show that the Area Delay Product(ADP) of the proposed 5-tap and 9-tap filter gains an improvement of 18.26% and 13.94%, respectively over the conventional method. Similarly, the Power Delay Product(PDP) is improved by 16.80% and 12.54%, respectively. © 2015 IEEE.