The objective of the work scheduled is to design an area-efficient filter bank in a digital hearing aid by making use of Verilog HDL for functional verification, Synthesis & Physical Design in Cadence- Genus & Innovus respectively using ASIC design flow. Hypoacusis is a medical term which is well referred to as hearing impairment is a total or partial incompetence to hear. Around 466 million people live with Hypoacusis worldwide this is over 5% of the world's populace. Hearing Aid is an Acoustoelectric Transducer which selectively enhances signal to ear to reimburse hearing loss. As technology is advancing day by day digital hearing aids are more adaptive, small and lightweight. The main block of the hearing aid is a filter bank which performs sound decomposition. To design a filter bank, it requires a precise intelligence of distinct digital signal processing approaches used in hearing aids among them the most important is to design a filter in which FIR, IIR, IFIR are crucial, which extracts signal within frequency bands. The proposed design area is minimized by 70.53%. thereby the size of the device is drastically reduced. The proposed design has an added advantage of lower power and delay. © 2021 Institute of Physics Publishing. All rights reserved.