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Design of Basic Building Blocks of ALU
, Sahoo S.K, Bharathi V, Devi A, Sarma R, Chowdary D.
Published in Springer India
Volume: 397
Pages: 315 - 327
There were no limits for speed of operation of arithmetic/logical circuits. One can always try to increase their speed. There were many proposed algorithms, which would work fast to specified arithmetic operations. So, there is the need for the implementation of a faster design by putting these fastest algorithms in a single ALU. The carry-select adder with K-S algorithm is found to be one of the fastest algorithms for addition and Urdhva-Tiryagbhyam Karastuba algorithm for multi- plication, which are the most important operations in any central processing unit. We have used QUARTUS-II software. This design can be used where high speed computation is needed. This design would work for unsigned, fixed point, 8-bit operations. We have taken the different adder circuits and compared their perfor- mance. These circuits are the basic elements or building blocks of an ALU. The circuits have been simulated using 90 nm technology of Cadence and Quartus II EP2C20F484C7. Adders can be implemented using EX-OR/EX-XNOR gates, transmission gates, HSD (High Speed Domino) technique, domino logic. Parallel feedback carry adder, ripple carry adder, carry look ahead adder, carry-select adder are some of the adders that been implemented using Cadence and Quartus-II. We found that 10T PFCA is efficient compared to 11 T PFCA to some extent. Adders © Springer India 2016.
About the journal
JournalData powered by TypesetProceedings of the International Conference on Soft Computing Systems Advances in Intelligent Systems and Computing
PublisherData powered by TypesetSpringer India
Open AccessNo