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Design of D flip-flops with pull up scheme and clock gating for input
V. Misra, Shubham,
Published in Blue Eyes Intelligence Engineering and Sciences Publication
Volume: 8
Issue: 6
Pages: 1784 - 1787
The following paper deals with a pulsed triggered flip-flop having a pull up control scheme. The flip-flop used is also incorporated with an embedded clock gating. The topology that has been used are the IPFF-CGPC Implicit Pulse Flip Flop with an embedded clock-gating and pull-up control scheme (IPFF-CGPC) and IPFF-ECGPC is the enhanced CGPC which arehaving XOR based gating clock.The main difference between the former and the latter is that it used a pass transistor based logic XOR for IPFF-CGPC and for latter XOR logic gating is based on the transmission gate. This topologies provide us with both novel approach and power efficiency is considerably high as in comparison to its other contemporary topologies The XOR gating in the pulse generation helps to disable the inverter chain during when the input is unchanged.Both the topologies helps to remove the redundant transistors of the internal node. Similarly the pull-up when transition is from D i.e from 0 to 1 saves the short-circuit power. In this paper further modification is done in the form of dynamic XOR gate used in the clock gating scheme which is further used to improve the performance of the Flip- Flop. The technology that we have used is 45nm feature size which function on a supply voltage of.8V and which further reducedthepowerandalsotheareaoftheFlip-Flop. © BEIESP.
About the journal
JournalInternational Journal of Innovative Technology and Exploring Engineering
PublisherBlue Eyes Intelligence Engineering and Sciences Publication