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Design of FinFET based All-Digital DLL for multiphase clock generation
Kumar M.K, Pasupathy K.R,
Published in IEEE
The use of delay locked loops (DLLs) for clock recovery is currently receiving an increased interest. Among the DLL types, the All-digital DLL is superior due to its tolerance towards power supply noise and PVT variations besides providing lesser locking time and technology portability. In this paper, All-Digital DLL based on register controlled delay line (RCDL) is designed for multi-phase clock generation using 30nm FinFET Technology. The RCDL consists of series of delay blocks which are in turn made up of FinFET inverters in series. The phase-delayed signal from the delay blocks is tapped using an AND gate and given to phase detector. According to the detected phase difference, the DLL adjusts the tap using a bidirectional shift register and locks the output signal with the reference clock. The circuit simulations of this work, are carried out by integrating the BSIM-CMG Verilog-A Model in Cadence Virtuoso EDA tool. The type of the device used is tri-gate FinFET and all the gates are connected to the same bias. The implemented DLL circuit exhibits fast locking in 9 clock cycles while operating at a frequency of 5GHz. Four accurate phases of reference clock are generated at a power consumption of 985 nW. © 2015 IEEE.
About the journal
JournalData powered by Typeset2015 Annual IEEE India Conference (INDICON)
PublisherData powered by TypesetIEEE
Open AccessNo