This paper presents FinFET-based Energy Efficient Pass Transistor Adiabatic Logic (EEPAL) powered by four-phase power clock capable of operating up to 1 GHz with low energy dissipation. Differential cascode adiabatic logic and pass transistor structure are employed. Furthermore, EEPAL employs discharge transistors assisting in eliminating floating output nodal issues of existing adiabatic circuits. Its efficiency is proved through half and full adder circuits constructed using FinFET-based 2N2P, 2N2N2P, Positive Feedback Adiabatic Logic (PFAL), Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) and Pass transistor Adiabatic Logic (PAL) based circuits. Carry Lookahead Adder (CLA) and Carry Save Multiplier (CSM) are used as benchmark circuits to validate the efficiency of EEPAL. Energetics of EEPAL and effect of parameter variations on energy dissipation have been derived and analyzed. BSIMCMG FinFET models have been used for simulations in Cadence® Virtuoso. At 500 MHz, 16-bit CSM designed using EEPAL is 25%, 34%, 21% and 12% energy efficient than CSM designed using 2N2P, 2N2N2P, PFAL and DCPAL. © 2019 Elsevier Ltd

V S Kanchana   Bhaaskaran

Electronics

School of Electronics Engineering

Chennai Campus

Bhuvana B.P

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Microelectronics Journal

Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications

In recent years, side channel attacks such as Differential Power Analysis (DPA) and Simple Power Analysis (SPA) are the most common in cryptographic hardware systems. Smart Cards, RFID tags, military communications and electronic commerce are some of the applications where cryptography plays a significant role. Adiabatic logic design is one among various low power VLSI design techniques used in the design of cryptographic hardware systems. In this paper, we propose the Positive Feedback Symmetric Adiabatic Logic (PFSAL) which reduces the energy dissipated by the S-Box circuit used in the cryptographic designs. Proposed PFSAL is validated by the design of the PFSAL based Rijndael S-Box. The efficiency of the proposed design is validated by comparing it with Rijndael S-Box designed using other existing security based adiabatic logic circuits. Results are simulated in Cadence Virtuoso. Proposed PFSAL is competent in terms of energy consumption, uniform power and current traces when compared with the existing counterparts. © 2018 IEEE.

2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID)

Positive Feedback Symmetric Adiabatic Logic Against Differential Power Attack

The novel pre-resolve and Sense Adiabatic Logic (PSAL) is a less complex quasi-adiabatic logic circuit usable for frequency range from 100 KHz to 500 MHz. It employs a large height pre-resolved nMOS structured tree and a differential sensing logic. The logic realizes superior energy efficiency through reduced silicon area requirement, low circuit latency, glitch-free output and less switching transients. Significant reduction in switched capacitance realizes enhanced speed performance. Furthermore, evaluation of more than one level of gate (or a complex gate) in each phase makes use of less number of buffers possible, in the adiabatic pipeline. With circuit latency being a major impediment of four-phase adiabatic logic styles, PSAL achieves better throughput and reduced critical path length leading to improved frequency performance. The nMOS structured cascode tree and differential sensing logic help overcome the incomplete charge-recovery and the floating output node problems prevalent in adiabatic logic structures. Full custom and modular flow is adopted in the circuit designs. The design is proved energy-efficient for both low and high frequency ranges of the order of 200 KHz and 500 MHz, respectively for an 8-bit multiplier. Full-custom designs are done using 350 nm CMOS technology library from Austria Micro Systems. Performance efficiency is proved through comparisons with static CMOS and PFAL equivalent circuits through extensive post-layout simulations.

Journal of Circuits, Systems and Computers

PRE-RESOLVE AND SENSE ADIABATIC LOGIC FOR 100 KHZ TO 500 MHZ FREQUENCY CLASSES

This paper presents the design and performance analysis of the dual-rail encoded and sense-amplifier structured 2N–2P, 2N–2N2P, IPGL and PFAL quasi-adiabatic circuits operated by two-phase sinusoidal power-clock sources. The energetics of these families are studied for varying power-clock voltages. The drivability characteristics are evaluated using capacitive loads. The performance validation is made through 8-bit and 16-bit adder circuits using an integrated power-clock generator. Optimal adiabatic gain values are achieved for 2N–2N2P and IPGL circuits across a wide frequency range. Energy recovery comparison between the four-phase ramp and two-phase sine power-clocks is made. The results demonstrate the efficiency of sinusoidal power clock at both the high and the low frequency ranges of operation. The circuits were designed using 180 nm CMOS technology.

TWO-PHASE SINUSOIDAL POWER-CLOCKED QUASI-ADIABATIC LOGIC CIRCUITS

This paper presents Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) that can operate with greater functionality, larger fan-in and high energy efficiency. It is a diode free and dual rail logic operated by four phase power clock for the adiabatic pipeline. Less complex with differential cascode structure and fewer numbers of transistors, the pre-resolving feature for the complementary inputs achieves reduction in latency, significant drop in the switched capacitance that realizes power efficiency, better silicon area efficiency, reduced leakage paths and glitch-free output with reduced switching transients. Energy efficiency against static CMOS equivalent and better speed performance against 2N2P, 2N2N2P, PFAL and IPGL equivalent circuits are proved. By the use of post-layout simulations of multi-bit adder and multiplier circuits adopted through full-custom circuit design, the DCPAL achieves adiabatic gain values in the range of 20.85 at 100 MHz power clock frequency to 9.88 at 500 MHz against the static CMOS equivalent 8-bit Wallace tree multiplier circuit. Energy saving of 50% and 45% is achieved against optimized 2N2N2P and PFAL 8-bit multiplier circuits at 500 MHz, and energy saving against these circuits enhances further at higher frequencies. Copyright © 2008 American Scientific Publishers All rights reserved.

Journal	Data powered by TypesetMicroelectronics Journal
Publisher	Data powered by TypesetElsevier BV
ISSN	0026-2692
Open Access	No