In this paper, we have presented a design of hybrid arithmetic logic unit (ALU) in Double precision format (DPF) according to the IEEE-754 standard. In this we have designed an ALU which consists of the two different architectures. First architecture is semi-floating point unit (Semi-FPU) and the second architecture is floating point unit (FPU). Semi-FPU takes a 32-bit integer input and produces an output in 64-bit DPF. And the floating point unit takes the input in 64-bit DPF and produces the output in 64-bit DPF. FPU also provides rounding and exception handling. Both the architectures can perform addition, subtraction, division, and multiplication. ALU is designed with three different adders which is ripple carry adder, carry lookahead adder, and carry save adder. The parameters such as area, power, and delay is compared for each modules (add, mul, div) of ALU with all three different adders. And according to the power-delay product, the best adder among the above three is chosen for each operation. The sub modules are written in Verilog HDL. For simulation we have used Xilinx ISE software and synthesis is done using cadence Encounter RTL compiler using typical libraries of TSMC 45 nm technology. © 2017 IEEE.