Flip-flop plays a major role in designing a synchronous circuits and memory. In this paper we have shown the comparison of performance for various circuits of flip flops, master-slave flip flops and transmission gates. FFs are mostly used to collect the group of data for a storage purpose and the performance includes delay, area minimization and power reduction. The delay can be minimized by transistor sizing and variation of voltage. The proposed circuits are simulated and compared using 90nm and 45nm technology. © 2016 IEEE.

Sakthivel R

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Lakshman V.K.A

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Design of high performance power efficient flip flops using transmission gates

2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)

With advent of technology scaling, the prime objective of design i.e. low power consumption can be easily acquired. For any digital logic design the power consumption depends on; Supply voltage, number of transistors incorporated in circuit and scaling ratios of the same. As CMOS technology supports inversion logic designs; NAND &amp; NOR structures are useful for converting any logic equation into physical level design that comprises of PMOS and NMOS transistors. In similar way, logic can be implemented in other styles as well, with the difference in number of transistors required. The conventional CMOS design for XOR logic can be possible with 8 or more than 8 transistors, with the methodology discussed in this paper, the same design for XOR logic can be made possible with 6 transistors. The proposed methodology consists of Pass transistor logic and Single feedback topology. This design consumes 50% less power than that of conventional XOR logic design with CMOS technology. Since the design for XOR logic, is useful for variety of applications such as Data encryption, Arithmetic circuits, Binary to Gray encoding etc. the XOR logic has been selected for design. The design explained in this paper is simulated with Cadence 90nm technology. © 2017 IEEE.

2017 Fourth International Conference on Signal Processing, Communication and Networking (ICSCN)

Low power XOR gate design and its applications

IEEE Journal of Solid-State Circuits

A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating

High-performance and low-power conditional discharge flip-flop

Conditional-capture flip-flop for statistical power reduction

Journal	Data powered by Typeset2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)
Publisher	Data powered by TypesetIEEE
Open Access	0