The filter proposed in this paper has an advantage of higher frequency response and better selectivity against the classical band pass filter. A Fully Differential Current (FDC) Conveyor has been designed and it uses the application of differential difference operational floating amplifier (DDOFA) and floating current source circuits. The circuit design is synthesized using 180nm CMOS technology with ±1.8V power supply in cadence virtuoso and the simulation is done using Spectre. The FDC Conveyor is to be used in the complex filter with 700MHz center frequency. Using cascading technique, another higher order complex filter at 700 MHz center frequency is proposed and it is now suitable for applications like Bluetooth receivers.The simulation results shows that the gain is programmable without altering the 'Q' value of the filter which makes FDC Conveyor suitable to implement as a VGA and FDC Conveyor-Based Band Pass filter is shown in our work. © 2013 IEEE.

Sakthivel R

Department of Micro and Nanoelectronics

School of Electronics Engineering

Vellore Campus

Vani N.S

Vincent D.L

Jeysingh D.

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Design of high quality factor fully-differential CMOS current conveyor for a complex filter application

2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT)

This paper presents about the design of a low power 10-bit 50-M sample /sec Sample and Hold amplifier. A sample and hold amplifier (SHA) acts as a front end block for an Analog Digital Circuit (ADC). To realize a low power SHA, a power efficient Operational Tran-conductance Amplifier (OTA) is to be designed and used. In the literature, many topologies of OTA are proposed for low power. In this paper, an Improved Recycling Folded Cascade (IRFC) OTA existing in the literature is used for realizing SHA and is proposed. In addition to this the SHA includes bottom plate sampling and bootstrap switch to reduce the non-linear distortion. The IRFC OTA used in the design of SHA is implemented using TSMC 90 nm Process. It achieves a DC gain of 73 dB, Unity Gain Bandwidth (UGB) of 70 MHz and with a phase margin of 63 degrees. The proposed SHA is designed and simulated using spectre simulator. From the simulation, it is noted that the SHA achieves a Spurious Free Dynamic Range (SFDR) of 63.44dB and SNDR of 60.6dB for a sampling frequency of 50MS/s with a peak-peak voltage of 1.2 Volts. The S/H circuit consumes 0.44mW of power. © 2018 Copyright is held by the owner/author(s).

Proceedings of the 2018 International Conference on Communication Engineering and Technology - ICCET '18

A Low Power 10 bit 50-MS/s Sample and Hold OTA Amplifier

2007 IEEE International Conference on Signal Processing and Communications

Low Voltage CMOS Fully Differential Current Feedback Amplifier with Controllable 3-dB Bandwidth

Analog Integrated Circuits and Signal Processing

Fully differential CMOS CCII based on differential difference transconductor

Fully Differential CMOS Current Feedback Operational Amplifier

Journal	Data powered by Typeset2013 International Conference on Circuits, Power and Computing Technologies (ICCPCT)
Publisher	Data powered by TypesetIEEE
Open Access	0