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Design of high speed DDR SDRAM controller with less logic utilization
P. Singh, B. Reniwal, , S.K. Vishvakarma
Published in Institute of Electrical and Electronics Engineers Inc.
This paper focuses on controlling synchronous dynamic random access memory (SDRAM) higher data transfer rates when multiple locations in internal memory array are accessed successively. The controller is designed to interface DDR memory modules and memory ICs with low cost FPGAs and high clock frequency of 674.491 MHz at 28nm technology on Kintex 7 FPGA device with less logic utilization. The DDR controller makes many low level tasks invisible to the user like refresh, initialization and timings. It provides another layer of abstraction by optimizing memory access for maximum throughput or minimum latency. DDR controller provides the access of memory banks in parallel form, so it is required to being fast with less logic utilization. This paper optimizes the DDR SDRAM controller design by structural RTL level HDL Coding and modelling of SDRAM Initializing finite state machine (FSM). The results show 0.33% of slice utilization and 0.14% of LUT utilization is recorded at Xilinx Virtex 7 low voltage FPGA device. Due to RTL level optimization the route delay is just about 30% to 38 % as compare to that of logic delay. We also observe that the Kintex 7 Xilinx FPGA device has low offset input and output delay of the clock clk100 and clk200 of data path in this logic as compare to other FPGA devices. So hereby we proposed a DDR SDRAM controller which can work at high speed with less logic utilization and minimum logic, route and offset delay. © 2014 IEEE.