Dynamic logic circuits are preferred over static logic circuits for their increased speed performance and lower power consumption. However, they are found prone to false evaluation while cascading multiple stages of dynamic logic circuits. To overcome this problem, the domino logic circuits were proposed by researchers. However, they offer reduced noise margins due to increased leakage current and charge sharing problems. In this paper, Manchester Carry Chain Adder design is explored for use with domino logic and comparison of various domino logic topologies intended for improved noise immunity and reduced leakage current against the proposed structure have been carried out. Wide fan-in gates and 8-bit Manchester Carry Chain Adder (MCC) based on various high speed domino logic circuit topologies have been designed using Cadence® using 180nm technology library from TSMC. Design of 8-bit OR gate, using High Speed Domino (HSD) topology consumes 10.8% lower power in comparison with Controlled-Current Comparison-based domino logic (C3D) topology. Furthermore, it is observed that an 8-bit Manchester Carry Chain adder using HSD topology is 5.027 times faster than C3D topology and the leakage power consumption is also reduced. © 2019 IOP Publishing Ltd. All rights reserved.