Flip-flops (FFs) are the basic storage elements used extensively in all kinds of digital designs. In particular, digital designs nowadays often adopt intensive pipelining techniques and employ many FF-rich modules such as register file, shift register, and first in- first out. In this paper we proposed a low power consumed and less area pulse triggered flip-flop. This design uses 23 transistors this reduces the area complexity by 3 transistors comparing with existing ep-DCO. The new flipflop can save up to 74% of the energy with the same speed as that for the existing ep-DCO and can save up to 69% of the energy with the same speed as that for the CDFF. © 2006-2015 Asian Research Publishing Network (ARPN).