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Design of optimal final adder for parallel multiplier
Published in IEEE
Pages: 436 - 441
The partial products in the normal multiplier is produced from the product of multiplier and the multiplicand, when considering the partial products the middle order take more time for final addition than considering the left and right side of the partial products, So to reduce the middle order partial product delay taking the optimal adder which is having high speed, on considering the BEC-1 adders Which has 3 types of architecture namely EBS, SBS and VBS. Analysis has been made on these adders both manually and experimentally to find out the optimal one in area, delay and power wise and to implement that as the final adder in the high delay path region. The experimental work has been done in typical case 180 nm technology for analyzing area, delay, power for BEC-1 adders. On analysis EBS shows better result manually and experimentally, So putting EBS adder in a unsigned multiplier using DADDA algorithm shows better result. © 2011 IEEE.
About the journal
JournalData powered by Typeset2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies
PublisherData powered by TypesetIEEE
Open AccessNo