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Design of quantum cost efficient reversible multiplier using Reed-Muller expressions
Published in Inderscience Publishers
Volume: 7
Issue: 3
Pages: 221 - 228

Reversible logic design is one of the emerging trends in recent years as it is good for low power design. A good number of design methods for reversible multipliers were proposed earlier. In this paper, two bit reversible multiplier was designed using Reed-Muller expressions, and this new reversible multiplier was used to design 4-bit reversible multiplier. The results save 16.9% of quantum cost (QC), 38.5% of garbage outputs (GOs) and 10.7% of constant inputs (CIs) compared to earlier designs. The simulations are done on Xilinx 10.1 and are presented. The methodology is extended for the design of 8-bit and 16-bit multipliers and the reversible logic metrics were presented for different bit lengths.

About the journal
JournalInternational Journal of Computing Science and Mathematics
PublisherInderscience Publishers
Open AccessNo