The keyword RISC stands for reduced instruction set computer. RISC architecture has become an important part of designing processors. This chapter discusses the designed processor using the Harvard architecture. This architecture has a different memory for data and instructions. Reduced complexity, a greater number of simpler instructions, pipelining and load–store architecture are the main advantages of this architecture. FPGAs have become of great importance to verify our proposed design. In this paper, Spartan 3E starter kit by Xilinx is used to perform the analysis of power and timing delays. The proposed processor has ALU unit, left barrel shifter, right barrel shifter and control unit. © 2021, Springer Nature Singapore Pte Ltd.