Cryptographic systems demand differential power analysis (DPA) resistant designs. The DPA resistance property of the Differential Cascode Pre-resolve Adiabatic logic (DCPAL) of quasi-adiabatic type of logic circuit is investigated in this paper. The DCPAL is an adiabatic logic, which incurs lower power consumption and earns its application in the design of low power cryptosystems. The property of power analysis resistance is demonstrated through the use of DCPAL implementation for a substitution-box (S-Box). The S-Box is implemented in both the standard CMOS and the DCPAL styles to prove the power analysis resistance and low-power operation capability. Fair comparisons have been made for validation. The advantage of using the DCPAL for DPA resistant systems is also demonstrated through the S-Box implementation. Extensive transient simulations have been carried out using the technology files from 180 nm foundry. © Springer Nature Singapore Pte Ltd. 2018.

Prathiba A

Electronics

School of Electronics Engineering

Chennai Campus

V S Kanchana   Bhaaskaran

K. M. Madhu

Vellore Institute of Technology (VIT) is a private university located in&nbsp;Tamil Nadu, India. Founded in 1984, as Vellore Engineering College, the institution offers 20 undergraduate, 34 postgraduate, four integrated and four research programs. It has campuses in Vellore, Amravati, Bhopal and Chennai.

VIT is one of the top ranked private universities in India according to NIRF, THE and QS Rankings.&nbsp;Govt. of India has recognized&nbsp;VIT, Vellore as an&nbsp;Institution of Eminence. This has allowed VIT to take independent quality initiatives and move up in world ranking.

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VIT University

Differential Power Analysis (DPA) Resistant Cryptographic S-Box

Lecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications

This paper presents Differential Cascode Pre-resolve Adiabatic Logic (DCPAL) that can operate with greater functionality, larger fan-in and high energy efficiency. It is a diode free and dual rail logic operated by four phase power clock for the adiabatic pipeline. Less complex with differential cascode structure and fewer numbers of transistors, the pre-resolving feature for the complementary inputs achieves reduction in latency, significant drop in the switched capacitance that realizes power efficiency, better silicon area efficiency, reduced leakage paths and glitch-free output with reduced switching transients. Energy efficiency against static CMOS equivalent and better speed performance against 2N2P, 2N2N2P, PFAL and IPGL equivalent circuits are proved. By the use of post-layout simulations of multi-bit adder and multiplier circuits adopted through full-custom circuit design, the DCPAL achieves adiabatic gain values in the range of 20.85 at 100 MHz power clock frequency to 9.88 at 500 MHz against the static CMOS equivalent 8-bit Wallace tree multiplier circuit. Energy saving of 50% and 45% is achieved against optimized 2N2N2P and PFAL 8-bit multiplier circuits at 500 MHz, and energy saving against these circuits enhances further at higher frequencies. Copyright © 2008 American Scientific Publishers All rights reserved.

Journal of Low Power Electronics

Differential Cascode Adiabatic Logic Structure for Low Power

Integration

Design exploration of a Symmetric Pass Gate Adiabatic Logic for energy-efficient and secure hardware

IEEE Transactions on Circuits and Systems I: Regular Papers

DPA-Secured Quasi-Adiabatic Logic (SQAL) for Low-Power Passive RFID Tags Employing S-Boxes

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

Process variation verification of low-power secure CSSAL AES S-box circuit

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Synthesis of Dual-Rail Adiabatic Logic for Low Power Security Applications

Journal	Data powered by TypesetLecture Notes in Electrical Engineering VLSI Design: Circuits, Systems and Applications
Publisher	Data powered by TypesetSpringer Singapore
ISSN	1876-1100
Open Access	0