Cryptographic systems demand differential power analysis (DPA) resistant designs. The DPA resistance property of the Differential Cascode Pre-resolve Adiabatic logic (DCPAL) of quasi-adiabatic type of logic circuit is investigated in this paper. The DCPAL is an adiabatic logic, which incurs lower power consumption and earns its application in the design of low power cryptosystems. The property of power analysis resistance is demonstrated through the use of DCPAL implementation for a substitution-box (S-Box). The S-Box is implemented in both the standard CMOS and the DCPAL styles to prove the power analysis resistance and low-power operation capability. Fair comparisons have been made for validation. The advantage of using the DCPAL for DPA resistant systems is also demonstrated through the S-Box implementation. Extensive transient simulations have been carried out using the technology files from 180 nm foundry. © Springer Nature Singapore Pte Ltd. 2018.