As the complexity of electronic systems increasing day by day, power consumption has emerged one of the main design constraints. In recent years, there has been increasing demand for high speed low power consumption electronic systems. Flip flops are critical timing elements in any electronic system. Here power consumption is reduced by reducing dynamic power consumption. In this paper, I proposed dual edge triggered flip flop for low power systems which will work as normal dual edge triggered flip flop. Reduction in the number of transistors along with double edge triggering technique helps to reduce power dissipation. Because of the property of dual edge triggering, circuit speed is doubled compared to single edge triggered flip flop. © Research India Publications.