The paper presents the design of 8-bit adder structures based on the Carry Look Ahead (CLA) and Carry Skip Adder (CSKA) architectures by employing the High Speed Clock Delayed (HSCD) domino logic. The paper presents the adder circuits constructed using dual threshold voltage devices and comparison have been made for the circuits while operating with normal Vth transistors to analyze the use of dual Vth devices. The high threshold voltage transistors are deployed in the non-critical paths and low threshold voltage transistors are deployed in the critical paths. The adder designs using the dual Vth HSCD technique for the CLA adder and CSKA offer reduced delay values of 98.4ps and 110.4ps respectively. The use of dual Vth makes the designs to operate with 18% less power consumption than the adder circuits designed using normal Vth. Furthermore, considerable leakage power reduction of 2.1 nW and 1.83 nW have been realized for the CLA and CSKA under Clock high Input low (CHIL) condition. Industry standard EDA tools have been employed for the simulations using 45nm GPDK libraries. © 2016 IEEE.