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Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETsPublished in Institute of Electrical and Electronics Engineers Inc.
2016
DOI: 10.1109/iNIS.2015.22
Pages: 243 - 247
Noise margin and delay are main concern to VLSI circuit designers along with the device scaling. Therefore, in this paper, the work on various double gate NMOS structures employing gate and channel engineering like gate stack, halo implant and work function engineering is presented. The comparison of threshold voltage, ON and OFF current of various device structures has been performed. Further, D.C. And transient analysis of resistive load inverter circuit using these devices have been investigated. Noise margin and delay of these circuits are also compared. In addition, Tied (3T) and independent (4T) gate configurations are also compared at device and circuit level. The result shows that the Tri-material gate stack (GS-TM) configuration is best structure suited for circuit design. The simulation and parameter extraction have been done using TCAD Silva co simulator. © 2015 IEEE.
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About the journal
| Journal | Data powered by TypesetProceedings - 2015 IEEE International Symposium on Nanoelectronic and Information Systems, iNIS 2015 |
|---|---|
| Publisher | Data powered by TypesetInstitute of Electrical and Electronics Engineers Inc. |
Authors (1)
Vikas Vijayvargiya- Dataline isolated differential current feed/mode sense amplifier for small Icell SRAM using FinFET
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