The need for real time high end digital signal/image processing demands a very huge computation with a reasonable accuracy. This paper presents two energy efficient low area error tolerant adders (ELAETA-I and ELAETA-II) which could cater the needs of most signal processing application. This work has reduced the tradeoff that exists between the amount of computation and the accuracy. The error sensitive block in the inaccurate part of the ELAETA circuit, predetermines the carry and allows the simultaneous calculation of inaccurate part sum value, thereby reducing the maximum delay by 55 % compared to error-tolerant adder (ETA-I) and its appropriate addition of carry to the accurate part increases the accuracy by 20 % over the existing ETA-I and ETA-II. The inaccurate part of the adder is being constructed with the proposed new OR gate cell and the pass transistor cell, which has reduced the number of transistor by 10 and 12, respectively, compared with the existing ETA-I. In addition a new data aware block has been included which will evaluate the input sequence and appropriately activate/de-activate certain computation modules and there by reduce the switching activity. The simulation result of the proposed ELAETA circuits shows that the power delay product has reduced by 59 % and area around 20 %. The whole circuit has been constructed using Cadence Virtuoso and the simulation done using Spectre with 180 and 45 nm technology node from TSMC. © 2014 Springer Science+Business Media New York.