The quasi-adiabatic switching circuits reclaim part of the energy spent in the computation process and recycle the recovered energy for subsequent computations. The efficiency of such circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. These losses, in turn, are dependent on the operating frequency, the unclaimed charge trapped in the floating internal circuit nodes, the charge sharing and the leakage effects. The technology used in the circuit design has an ultimate effect on the factors mentioned above. This paper presents the modeling and performance efficiency analysis of the sense-amplifier based quasi-adiabatic structures, namely, the 2N-2P, 2N-2N2P, PFAL and the DCPAL circuits using Berkeley Predictive Technology Models (BPTM). The viability of the design of adiabatic circuits using the 65 nm, 45 nm and 32 nm BPTM is illustrated. The performance is analyzed by comparing with that obtained using full-custom designed circuits using the 350 nm process technology node from Austria Micro Systems. Extensive simulations result in gain values from 20.9 to 10.8 against CMOS counterparts across a frequency range of 200 kHz to 1 GHz. ©2011 IEEE.