In the high demand of electronics such as mobile, tablets there is increase in the demand for high speed, good battery life and high storage. As it is common notion that power and speed always form inverse relation thus compromising on one factor is acceptable to customers. But area that is storage is a demanding factor and in order to achieve such high storage, Technology is shrinking down drastically (currently at 7nm) and expected to go even lower. With this shrinking of technology the need for detecting manufacturing defects becomes important and thus DFT architecture and regress pattern simulations become necessary factor. Our objective here is to reduce the time required for regress pattern simulations by improving the simulation infrastructure. Our results could observe reduction in the simulation time by 18-20 percentages in VCS tool. © 2018 IEEE.